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june 2010 doc id 13446 rev 3 1/22 22 ld49150xx08 ld49150xx10, ld49150xx12 1.5 a very low drop for lo w output voltage regulator features input voltage range: ?v i = 1.4 v to 5.5 v ?v bias = 3 v to 6 v stable with ceramic capacitor 1.5 % initial tolerance maximum dropout voltage (v i - v o ) of 200 mv over temperature adjustable output voltage down to 0.8 v ultra fast transient response (up to 10 mhz bandwidth) excellent line and load regulation specifications logic controlled shutdown option thermal shutdown and current limit protection junction temperature range: - 25 c to 125 c applications graphics processors pc add-in cards microprocessor core voltage supply low voltage digital ics high efficiency linear power supplies smps post regulators description the ld49150xx is a high-bandwidth, low-dropout, 1.5 a voltage regulator, ideal for powering core voltages of low-power microprocessors. the ld49150xx implements a dual supply configuration allowing for very low output impedance and very fast transient response. the ld49150xx requires a bias input supply and a main input supply, allowing for ultra-low input voltages on the main supply rail. the input supply operates from 1.4 v to 5.5 v and the bias supply requires between 3 v and 6 v for proper operation. the ld49150xx offers fixed output voltages from 0.8 v to 1.8 v and adjustable output voltages down to 0.8 v. the ld49150xx requires a minimum output capacitance for stability, and work optimally with small ceramic capacitors. ppak dfn6 (3x3 mm) table 1. device summary order codes output voltages ppak (tape and reel) dfn6 (tape and reel) (1) ld49150pt08r 0.8 v (2) LD49150PT10R ld49150pu10r 1.0 v ld49150pt12r ld49150pu12r 1.2 v 1. available on request. 2. adjustable version. www.st.com
contents ld49150xx08, ld49150xx10, ld49150xx12 2/22 doc id 13446 rev 3 contents 1 typical application circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 alternative application ci rcuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 7 typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.1 input supply voltage (v in ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.2 bias supply voltage (v bias ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.3 external capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.4 output capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.5 minimum load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.6 power sequencing recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.7 power dissipation/heatsinking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 8.8 heatsinking ppak package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.9 adjustable regulator design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 8.10 enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
ld49150xx08, ld49150xx10, ld49150xx12 typical application circuits doc id 13446 rev 3 3/22 1 typical application circuits figure 1. adjustable version figure 2. fixed version with enable
alternative application circuits ld49150xx08, ld49150xx10, ld49150xx12 4/22 doc id 13446 rev 3 2 alternative application circuits figure 3. single supply voltage solution figure 4. ld49150xx plus dc-dc pre-regulator to reduce power dissipation
ld49150xx08, ld49150xx10, ld49150xx12 pin configuration doc id 13446 rev 3 5/22 3 pin configuration figure 5. pin connections (top view for ppak, bottom view for dfn) ppak dfn6 (3 x 3 mm) table 2. pin description pin n for ppak pin n for dfn symbol note 12 en for fixed versions: enable (input) - logic high = enable, logic low = shutdown. adj for adjustable versions: adjustable regulator feedback input. connect to resistor voltage divider. 23v in input voltage which supplies current to the output power device. 3 1 gnd ground (tab is connected to ground). 44v out regulator output. 56v bias input bias voltage for powering all circuitry on the regulator with the exception of the output power device. 5 n.c. not connect.
diagram ld49150xx08, ld49150xx10, ld49150xx12 6/22 doc id 13446 rev 3 4 diagram figure 6. block diagram
ld49150xx08, ld49150xx10, ld49150xx12 maximum ratings doc id 13446 rev 3 7/22 5 maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings (1) 1. all the values are referred to ground. symbol parameter value unit v in supply voltage -0.3 to 7 v v out output voltage -0.3 to v in + 0.3 -0.3 to v bias + 0.3 v v bias bias supply voltage -0.3 to 7 v v en enable input voltage -0.3 to 7 v p d power dissipation internally limited t stg storage temperature range -50 to 150 c table 4. operating ratings symbol parameter value unit v in supply voltage 1.4 to 5.5 v v out output voltage 0.8 to 4.5 v v bias bias supply voltage 3 to 6 v v en enable input voltage 0 to v bias v t j junction temperature range -25 to 125 c
electrical characteristics ld49150xx08, ld49150xx10, ld49150xx12 8/22 doc id 13446 rev 3 6 electrical characteristics t j = - 25 c to 125 c, v bias = v o + 2.1 v (1) ; v i = v o +1 v; v en = v bias (2) , i o = 10 ma; c i = 1 f; c o = 10 f; c bias = 1 f; unless otherwise specified. typical values are referred to t j = 25 c. table 5. electrical characteristics symbol parameter test conditions min. typ. max. unit v o output voltage accuracy t j = 25 c, fixed voltage options -1.5 1.5 % over temperature range -3 3 v line line regulation v i = v o + 1 v to 5.5 v -0.1 0.1 %/v v load load regulation i l = 0 ma to 3 a, v bias 3 v 1 % v drop dropout voltage (v i - v o )i l = 1.5 a 200 mv v drop dropout voltage (v bias - v o )i l = 1.5 a (1) 1.5 2.1 v i gnd ground pin current i l = 0 ma 4 6 ma i l = 1.5 a 4 6 i gnd_shd ground pin current in shutdown v en 0.4 v (2) 5a i vbias current through v bias i l = 0 ma 3 5 ma i l = 1.5 a 3 5 i l current limit v o = 0 v 2.5 a enable input (2) v en enable input threshold (fixed voltage only) regulator enable 1.4 v regulator shutdown 0.4 i en enable pin input current 0.1 1 a reference v ref reference voltage t j = 25 c 0.788 0.8 0.812 v over temperature range 0.776 0.8 0.824 svr supply voltage rejection v i = 2.5 v 0.5 v, v o = 1 v, f = 120 hz, v bias = 3.3 v 68 db 1. for v o 1 v, v bias dropout specification does not apply due to a minimum 3 v v bias input. 2. fixed output voltage version only.
ld49150xx08, ld49150xx10, ld49150xx12 typical characteristics doc id 13446 rev 3 9/22 7 typical characteristics figure 7. reference voltage vs. temperature figure 8. output voltage vs. temperature figure 9. load regulation vs. temperature fi gure 10. line regulation vs. temperature figure 11. output voltage vs. input voltage figure 12. dropout voltage (v in -v out ) vs. temperature
typical characteristics ld49150xx08, ld49150xx10, ld49150xx12 10/22 doc id 13446 rev 3 figure 13. dropout voltage (v in -v out ) vs. temperature figure 14. v bias pin current vs. temperature figure 15. noise vs. frequency figure 16. quiescent current vs. temperature figure 17. supply voltage rejection vs. output current figure 18. stability region vs. c out & high esr
ld49150xx08, ld49150xx10, ld49150xx12 typical characteristics doc id 13446 rev 3 11/22 figure 19. stability region vs. c out & low esr figure 20. v bias & v in start up transient response (v in and v bias start up at the same time) v in =v bias =v inh =3.1v, v out =1v, c out =1f figure 21. v in start up transient response (v bias start up before v in ) figure 22. v in start up transient response (v bias start up before v in ) v in =2.5v, v bias =v inh =3.1v, v out =1v, c out =1f v in =2.5v, v bias =v inh =3.1v, v out =1v, c out =1f
typical characteristics ld49150xx08, ld49150xx10, ld49150xx12 12/22 doc id 13446 rev 3 figure 23. v in start up transient response (v bias start up before v in and v inh =v in ) v in =v inh =2.5v, v bias =3.1v, v out =1v, c out =1f
ld49150xx08, ld49150xx10, ld49150xx12 application hints doc id 13446 rev 3 13/22 8 application hints the ld49150xx is an ultra-high performance, low dropout linear regulator, designed for high current application that requires fast transient response. the ld49150xx operates from two input voltages, to reduce dropout voltage. the ld49150xx is designed so that a minimum of external component are necessary. 8.1 input supply voltage (v in ) v in provides the power input current to the ld49150xx. the minimum input voltage can be as low as 1.4 v, allowing conversion from very low voltage supplies to achieve low output voltage levels with very low power dissipation. 8.2 bias supply voltage (v bias ) the ld49150xx control circuitry is supplied the v bias pin which requires a very low bias current (3 ma typ.) even at the maximum output current level (1.5 a). a bypass capacitor on the bias pin is recommended to improve the performance of the ld49150xx during line and load transient. the small ce ramic capacitor from v bias to ground reduces high frequency noise that could be injected into the control circuitry from the bias rail. in typical applications a 1 f ceramic chip capacitor may be used. the v bias input voltage must be 2.1 v above the output voltage, with a minimum v bias input voltage of 3 v. 8.3 external capacitors to assure regulator stability, input and output capacitors are required as shown in the 1: typical application circuits . 8.4 output capacitor the ld49150xx requires a minimum output capaci tance to maintain stab ility. a ceramic chip capacitor of at least 1 f is required. however, specific capacitor selection could be needed to ensure the transient response. a 1 f cerami c chip capacitor satisf ies most applications but 10 f is recommended to ensure better tr ansient performances. in applications where the v in level is close to the maximum operating voltage (v in > 4 v), it is strongly recommended to use an output capacitors of, at least, 10 f in order to avoid over-voltage stress on the input/output power pins during short circuit conditions due to parasitic inductive effect. the output capacitor must be located as close as possible to the output pin of the ld49150xx. the esr (equivalent series resistance) of the output capacitor must be within the "stable" region as shown in the typical characteristics figures. both ceramic and tantalum capacitors are suitable. 8.5 minimum load current the ld49150xx does not require a minimum load to maintain output voltage regulation.
application hints ld49150xx08, ld49150xx10, ld49150xx12 14/22 doc id 13446 rev 3 8.6 power sequencing recommendations in order to ensure the correct biasing and settling of the regulator internal circuitry during the startup phase, as well as to avoid overvoltage spikes at the output, it is recommended to provide for the correct power sequencing. as a general rule the v in and v inh signals timings at startup should be chosen properly, so that they are applied to the device after the v bias voltage is already settled at its minimum operative value (see paragraph 8.2: bias supply voltage (vbias) ). this can be achieved, for instance, by avoiding too slow v bias rising edges (t r >10 ms). provided that the above condition is satisfied, when fast v in transient input (t r < 100 s) is present, a smooth startup, with limited overvoltage on the output, can be obtained by applying v in voltage at the same time as the v bias voltage (refer to figure 20 , figure 21 and figure 22 on page 11 ). in the fixed voltage versions it is possible to reduce overvoltage spikes during very fast startup (t r << 100 s) by pulling the v inh pin up to v in voltage (see figure 23 on page 12 ). 8.7 power dissipation/heatsinking a heatsink may be required depending on the maximum power dissipation and maximum ambient temperature of the application. under all possible conditions, the junction temperature must be within the range specified under operating conditions. the total power dissipation of the device is given by: p d = v in x i in + v bias x i bias - v out x i out where: v in , input supply voltage v bias , bias supply voltage v out , output voltage i out , load current from this data, we can calculate the thermal resistance ( sa ) required for the heat sink using the following formula: sa = (t j - t a /p d ) - ( jc + cs ) the maximum allowed temperature rise (t rmax ) depends on the maximum ambient temperature (t amax ) of the application, and the maximum allowable junction temperature (t jmax ): t rmax = t jmax - t amax the maximum allowable value for junction to ambient thermal resistance, ja , can be calculated using the formula: jamax = t rmax / p d this part is available for the ppak package. the thermal resistance depends on the amount of copper area or heat sink, and on air flow. if the maximum allowable value of ja calculated above is 100 c/w for the ppak package, no heatsink is needed since the package can dissipate enough heat to satisfy these requirements. if the value for allowable ja falls below these limits, a heat sink is required as described below.
ld49150xx08, ld49150xx10, ld49150xx12 application hints doc id 13446 rev 3 15/22 8.8 heatsinking ppak package the ppak package uses the copper plane on the pcb as a heatsink. the tab of these packages is soldered to the copper plane for he at sinking. it is also possible to use the pcb ground plane a heatsink. this area can be the inner gnd layer of a multi-layer pcb, or, in a dual layer pcb, it can be an unbroken gnd area on the opposite side where the ic is situated with a dissipating area thermally co nnected through vias holes, filled by solder. figure 26 shows a curve for ja of the ppak package for different copper area sizes, using a typical pcb with 1/16 in thick g10/fr4. 8.9 adjustable regulator design the ld49150xx adjustable version allows fixing output voltage anywhere between 0.8 v and 4.5 v using two resistors as shown in the typical application circuit. for example, to fix the r 1 resistor value between v out and the adj pin, the resistor value between adj and gnd (r 2 ) is calculated by: r 2 = r 1 [0.8/(v out - 0.8)] where v out is the desired output voltage. it is suggested to use r1 values lower than 10 k to obtain better load transient performances. even, higher values up to 100 k are suitable. 8.10 enable the fixed output voltage versions of ld49150xx feature an active high enable input (en) that allows on-off control of the regulator. the en input threshold is guaranteed between 0.4 v and 1.4 v, for simple logic interfacing. the regulator is set in shut down mode when v en < 0.4 v and it is in operating mode (v out activated) when v en > 1.4 v. if not in use, the en pin must be tied directly to the v in to keep the regulator continuously activated. the en pin must not be left at high impedance. figure 24. ja vs. copper area for ppak package
package mechanical data ld49150xx08, ld49150xx10, ld49150xx12 16/22 doc id 13446 rev 3 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com . ecopack ? is an st trademark.
ld49150xx08, ld49150xx10, ld49150xx12 package mechanical data doc id 13446 rev 3 17/22 dim. mm. inch. min. typ. max. min. typ. max. a 2.2 2.4 0.0 8 6 0.0 9 4 a1 0. 9 1.1 0.0 3 5 0.04 3 a2 0.0 3 0.2 3 0.001 0.00 9 b 0.4 0.6 0.015 0.02 3 b2 5.2 5.4 0.204 0.212 c 0.45 0.6 0.017 0.02 3 c2 0.4 8 0.6 0.01 9 0.02 3 d 6 6.2 0.2 3 6 0.244 d1 5.1 0.201 e 6.4 6.6 0.252 0.260 e1 4.7 0.1 8 5 e 1.27 0.050 g4. 9 5.25 0.1 93 0.206 g1 2. 38 2.7 0.0 93 0.106 h 9 . 3 5 10.1 0. 3 6 8 0. 39 7 l2 0. 8 1 0.0 3 1 0.0 39 l4 0.6 1 0.02 3 0.0 39 l5 1 0.0 39 l6 2. 8 0.110 ppak mechanical data 007 8 1 8 0-e
package mechanical data ld49150xx08, ld49150xx10, ld49150xx12 18/22 doc id 13446 rev 3 dim. mm. inch. min. typ. max. min. typ. max. a0. 8 00. 9 0 1.00 0.0 3 1 0.0 3 5 0.0 39 a1 0 0.02 0.05 0 0.001 0.002 a 3 0.20 0.00 8 b 0.2 3 0. 3 00. 38 0.00 9 0.012 0.015 d2. 9 0 3 .00 3 .10 0.114 0.11 8 0.122 d2 2.2 3 2. 38 2.4 8 0.0 88 0.0 9 4 0.0 98 e2. 9 0 3 .00 3 .10 0.114 0.11 8 0.122 e2 1.50 1.65 1.75 0.05 9 0.065 0.06 9 e0. 9 50.0 3 7 l0. 3 0 0.40 0.50 0.012 0.016 0.020 dfn6 ( 3 x 3 mm) mechanical data 7 9 466 3 7a
ld49150xx08, ld49150xx10, ld49150xx12 package mechanical data doc id 13446 rev 3 19/22 dim. mm. inch. min. typ. max. min. typ. max. a 33 0 12. 99 2 c12. 8 1 3 .0 1 3 .2 0.504 0.512 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t22.40. 88 2 ao 6. 8 06. 9 0 7.00 0.26 8 0.272 0.2.76 bo 10.40 10.50 10.60 0.40 9 0.41 3 0.417 ko 2.55 2.65 2.75 0.100 0.104 0.105 po 3 . 9 4.0 4.1 0.15 3 0.157 0.161 p7. 98 .0 8 .1 0. 3 11 0. 3 15 0. 3 1 9 tape & reel dpak-ppak mechanical data
package mechanical data ld49150xx08, ld49150xx10, ld49150xx12 20/22 doc id 13446 rev 3 dim. mm. inch. min. typ. max. min. typ. max. a1 8 0 7.0 8 7 c 12. 8 1 3 .2 0.504 0.51 9 d 20.2 0.7 9 5 n60 2. 3 62 t 14.4 0.567 ao 3 . 3 0.1 3 0 bo 3 . 3 0.1 3 0 ko 1.1 0.04 3 po 4 0.157 p 8 0. 3 15 tape & reel qfnxx/dfnxx ( 3 x 3 ) mechanical data
ld49150xx08, ld49150xx10, ld49150xx12 revision history doc id 13446 rev 3 21/22 10 revision history table 6. document revision history date revision changes 18-apr-2007 1 initial release. 12-jan-2009 2 added new package dfn6 (3x3 mm) and mechanical data. 29-jun-2010 3 modified section 8.6: power sequencing recommendations on page 14 .
ld49150xx08, ld49150xx10, ld49150xx12 22/22 doc id 13446 rev 3 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2010 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

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